Symmetric and complementary differential amplifier
US6822513B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2003 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | May 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45644
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A complementary differential amplifier includes two differential amplifiers. Each differential amplifier includes two input FETs (or bipolar transistors) having gate terminals coupled to the input terminals of the complementary differential amplifier. Two current load p-type field-effect transistors are each coupled in series between one voltage source and a drain terminal of a respective input FET. A current source FET is coupled in series between a common source terminal of the two input n-type field-effect transistors and a low voltage source. Only two FETs are needed to bias all of the current load and source FETs. A complementary folded cascode stage as well as an inverter stage may also be included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.