Circuits and methods for generating high frequency extended test pattern data from low frequency test pattern data input to an integrated circuit memory device
US6822914B2 · kind B2 · utility
1Cited by
6References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2003 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Jun 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory device includes a test pattern data generator circuit that is configured to generate an extended test pattern data based on test pattern data provided to the memory device during a test mode of the memory device and is configured to provide the extended test pattern data and the test pattern data during a test mode of the memory device. Related methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.