SRAM-compatible memory device employing DRAM cells
US6822920B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2003 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Aug 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a synchronous SRAM-compatible memory using DRAM cells. In the synchronous SRAM-compatible memory of the present invention, a refresh operation is controlled in response to a refresh clock signal having a period “n” times a period of a reference clock signal. The refresh operation is performed while a chip enable signal/CS is inactivated. A writing/reading access operation is performed in response to a writing/reading command generated while the chip enable signal/CS is activated. Therefore, in the writing/reading access operation of the synchronous SRAM-compatible memory of the present invention, no delay of time occurs that would otherwise occur due to the refresh operation of the DRAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.