Enhancing performance by pre-fetching and caching data directly in a communication processor's register set
US6822959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2001 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Nov 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry to free the core processor from performing the explicit read operation required to read data into the internal register set. The processor's register set is expanded and a “shadow register” set is provided. While the core processor is processing one event the “context” and “data” and other associated information for the next event is loaded into the shadow register set. When the core processor finishes processing an event, the core processor switches to the shadow register set and it can begin processing the next event immediately. With short service routines, there might not be time to fully pre-fetch the “context” and “data” associated with the next event before the current event ends. In this case, the core processor still starts processing the next event and the pre-fetch continues during the event processing. If the core processor accesses a register which is associated with part of the context for which the pre-fetch is still in progress the core processor will automatically stall or delay until the pre-fetch has completed reading the appropriate data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.