Operating system coordinated thermal management
US6823240B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2001 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor's performance state may be adjusted based on processor temperature. On transitions to a lower performance state due to the processor getting hotter, the processor's frequency is reduced prior to reducing the processor voltage. Thus, the processor's performance, as seen by the operating system, is reduced immediately. Conversely, on transitions to a higher performance state, due to the processor cooling down, the processor's frequency is not increased until the voltage is changed to a higher level. An interrupt event may be generated anytime the processor's phase locked loop relocks at a new frequency level. Thus, when the interrupt fires, the operating system can read the processor's performance state. As a result, interrupts are not generated that would cause processor performance to lag the interrupt event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.