Apparatus and method for distribution of signals from a high level data link controller to multiple digital signal processor cores
US6823402B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2001 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Dec 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem. In response to a predetermined condition, the signal groups are forwarded to the identified digital signal processor subsystem. The channel block unit, in response to preselected signal groups, can direct the packet to a digital signal processor subsystem that is different …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.