System and method for arbitration of a plurality of processing modules
US6823412B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2002 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Jun 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/70702
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for an arbitrated high speed control data bus system providing high speed communications between microprocessor modules in a complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocol. Bur arbitration is performed over a dedicated, independent, serial arbitration line. Each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions, eliminating the need for both bus request and bus grant signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.