Method, apparatus, and system for maintaining conflict-free memory address space for input/output memory subsystems
US6823421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2002 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Apr 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment of the present invention, an apparatus is provided which includes a first address translation unit and a second address translation unit. The first address translation unit is programmed for a minimum amount of memory addresses required to accept control transactions on a first bus. The second address translation unit is programmed to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory space required by the I/O interconnect device. The apparatus includes logic to determine, upon receiving an incoming host request, whether a reply address corresponding to the host request overlaps with the memory address range programmed for the second address translation unit. The apparatus further includes logic to dynamically alter a data flow between the first I/O interconnect device and the host.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.