Method and apparatus for load distribution across memory banks with constrained access
US6823432B2 · kind B2 · utility
Inventors
Key dates
| Filing date | May 28, 2002 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | May 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for load distribution across memory banks with constrained access is accomplished using a bank balancer that ensures that data to be buffered is evenly distributed throughout the various banks of the memory structure. The bank balancer maintains bank depth information relating to each of the banks. The bank balancer receives dequeue and enqueue information, where the dequeue information specifies read operations that will remove data from the various banks, and the enqueue information indicates that there is data to be written to the memory banks. The dequeue information constrains which banks may be utilized to enqueue received data. In order to determine to which banks to enqueue data, the bank balancer sorts the banks by their depth. The bank balancer then eliminates those banks which cannot be used for enqueue operations due to either the dequeue operations or other enqueue operations that have already been determined. Once a sorted list of eligible banks for enqueuing has been established, the bank balancer selects the bank storing the least amount of data which is eligible. The depth information for each bank is updated based on the enqueue and dequeue …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.