Exception handling using an exception pipeline in a pipelined processor
US6823448B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 15, 2000 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Sep 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The execution and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.