Lateral DMOS transistor with a self-aligned drain region
US6825531B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2003 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Jul 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
Abstract
An LDMOS transistor includes a body region, a source region, a conductive gate, an alignment structure and a drain region. The conductive gate is insulated from the semiconductor layer by a dielectric layer and overlies the body region. The source region is formed in the body region and is formed self-aligned to a first edge of the conductive gate. The alignment structure is formed adjacent a second edge, opposite the first edge, of the conductive gate. The alignment structure has a first edge in proximity to the second edge of the conductive gate. The drain region is formed in the semiconductor layer self-aligned to the second edge, opposite the first edge, of the alignment structure. The alignment structure can be formed in a polysilicon layer or a dielectric layer. The incorporation of the alignment structure in the LDMOS transistor enables self-aligned drain region or drain contact opening to be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.