Charge pump circuit, passive buffer that employs the charge pump circuit, and pass gate that employs the charge pump circuit
US6825699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2003 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Jan 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Buffer that includes an input node, an output node, and a three-transistor charge pump circuit is coupled to the input node and the output node. The buffer generates an output signal that is a delayed version of a signal presented at the input node. The three-transistor charge pump includes a first transistor (e.g., a pass transistor) that includes a drain electrode that is coupled to the input node, a gate electrode and a source electrode; a second transistor that includes a drain electrode that is coupled to a first predetermined voltage, a gate electrode coupled to the drain electrode of the second transistor, and a source electrode coupled to the gate electrode of the first transistor; and a capacitive element that includes a first electrode that is coupled to the source electrode of the second transistor and the gate electrode of the first transistor and a second electrode that is coupled to the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.