Clock signal generation circuit and audio data processing apparatus
US6825705B2 · kind B2 · utility
1Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2003 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Jun 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generation apparatus includes a first clock generation circuit which generates a clock signal by making state transition in synchronization with a master clock signal after exiting from a predetermined state in response to a timing signal supplied from an exterior of the apparatus, a counter which counts clock pulses of the master clock signal after exiting from a reset state in response to the timing signal, and a reset circuit which resets the counter and sets the first clock generation circuit in the predetermined state in response to the count of the counter reaching a first predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.