Multiplexer
US6825706B2 · kind B2 · utility
1Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2003 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Mar 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/047
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A multiplexer containing multiple cells sharing a common output line. The cells select one of multiple input bits. The output line is first charged to a first logical value (e.g., 0), and one of the cells drives the output line to a second logical value (1) if the corresponding input bit does not equal the first logical value. The remaining cells may not affect the output line. Due to such an implementation, the number of transistors may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.