Current mirror for an integrated circuit
US6825710B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 2003 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Apr 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An integrated circuit arrangement comprising a reference-current source device for providing a reference current (Iin) and comprising a current mirror device for mirroring the reference current (Iin) to an output current (Iout), wherein the current mirror device comprises a first FET (Q1), operated in saturation, whose channel carries the reference current; as well as a second FET (Q2), operated in saturation, whose channel carries the output current, wherein the gate connections of the two FETs (Q1, Q2) are interconnected in order to ensure identical control voltages (Vgs) at these two FETs (Q1, Q2), wherein at a channel connection of the first FET (Q1), a node for generating the reference current (Iin) carried by the channel of this FET is provided from several reference-current components (Iin1, Iin2), wherein the reference-current components are provided at the node by the reference-current source device, and one (Iin2) of the reference-current components (Iin1, Iin2) is carried by way of a resistance element (Qr) which is connected between the node and the gate connection of the first FET (Q1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.