Amplifier gain boost circuitry and method
US6825721B2 · kind B2 · utility
13Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2002 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Apr 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45682
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.