Virtual frame buffer control system
US6825845B2 · kind B2 · utility
8Cited by
9References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2002 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Jul 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/14
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A Virtual Frame Buffer control system and method for cascading several display controllers on one LCD panel. The Virtual Frame Buffer is composed of all the memory in all the controller/memory/source driver chips (in a tiled pattern) for the associated processor to read and write in. The control system also includes hardware clipping controls in each of the controller/memory/source driver chips. The Virtual Frame Buffer and hardware clipping control placement substantially reduces programming problems associated with prior art solutions for cascading LCD controller/memory/source driver devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.