Multiplex bucket brigade circuit
US6825877B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2000 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Jan 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/711
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A sensor chip assembly time delay integration circuit useful with image sensing arrays uses a duplex bucket brigade circuit (120) with two or more charge transfer paths, a number of capacitors (130, 133, 136) common to the charge transfer paths, and a number of capacitors (131, 132, 134, 135) specific to each of the charge transfer paths. Each of the charge transfer paths has a number of MOSFET transfer gates (122, 124, 126, 128; 123, 125, 127, 129) connected in series, and the common capacitors and the path-specific capacitors are alternately connected to the paths. Each of the common capacitors is controllably connected (112, 115, 118) either to a unit cell input circuit (113, 116, 119). a reset node (111, 114, 117), or an open circuit. The circuit operates by storing accumulated image sensor charges from alternate sensor lines on the path-specific capacitors. The common capacitors are reset and then connected to the unit cell input circuits to acquire a first set of image sensor charges. Charges stored on, for example, the capacitors of a particular path are then transferred to the common capacitors through transfer gates, in effect accumulating charge on the common capacitors. …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.