Semiconductor memory device including page latch circuit
US6826116B2 · kind B2 · utility
28Cited by
15References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2004 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Jan 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.