Communication packet processor with a look-up engine and content-addressable memory for storing summation blocks of context information for a core processor
US6826180B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2001 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Jun 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/7453
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Packet processing circuitry comprises a processor and a look-up engine. For a first communication packet, the look-up engine transfers a first selector to a CAM and receives a corresponding first result from the CAM, retrieves a first context structure based on the first result and builds a summation block using the first context structure, transfers the summation block to the processor, writes a second selector to the CAM and receives a corresponding second result from the CAM, and writes the summation block to a memory location corresponding to the second result. For a second communication packet, the look-up engine transfers the second selector to the CAM and receives the corresponding second result from the CAM, retrieves the summation block based on the second result and transfers the summation block to the processor The processor receives and processes the summation block to control handling of the first and second communication packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.