Phase locked loop with control voltage centering
US6826246B1 · kind B1 · utility
13Cited by
10References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1999 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Oct 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) with reduced jitter is provided. The PLL includes dual path voltage-controlled oscillator inputs, with a control voltage from a loop filter sent through a low gain path and an integrated error voltage sent through a high gain path. The error voltage is derived from the difference between a reference value representing averaged control voltage and a predetermined portion of the control voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.