Clock divider with error detection and reset capabilities
US6826250B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2001 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Apr 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1403
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for generating a divided clock signal. A ring counter is provided with a sequence of output states. During steady-state operation, a different one of the output states is set at a first logical level and each of the remaining output states is set at a second logical level at each successive clock transition in a master clock signal. A gate network uses the respective logical levels of the output states to generate the divided clock signal. An error detection circuit outputs an error detection signal when a number of the output states at the first logical level is other than one, and proceeds to synchronously reset the ring counter when the error condition is detected. A programmable processor further asynchronously resets the ring counter in response to the error detection signal, as desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.