Method, system and computer product for performing geometric dimension and tolerance stack-up analysis
US6826510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2002 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Jun 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/12
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method for performing geometric dimension and tolerance stack-up analysis for an assembly, the method comprising receiving a target assembly dimension for stack-up analysis, where the assembly includes at least one part. The method further comprises receiving a feature corresponding to the part and receiving feature tolerance data associated with the feature. The feature tolerance data includes at least one of size tolerance and geometric tolerance. Stack-up rules are accessed in response to receiving the feature tolerance data. The stack-up rules include instructions to determine if a form tolerance, an orientation tolerance and a profile tolerance should be included in a stack-up tolerance for the feature. The stack-up rules also include formulas to calculate a nominal dimension and the stack-up tolerance for the feature when the feature tolerance data applies to features of sizes. The nominal dimension and the stack-up tolerance are derived in response to the stack-up rules and the feature tolerance data. Stack-up analysis is performed in response to the nominal dimension and the stack-up tolerance. Performing stack-up analysis results in a mean and standard deviation for the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.