Reconfiguration method applicable to an array of identical functional elements
US6826709B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Oct 7, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17343
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention relates to a method for reconfiguring a network of parallel functional elements tolerant to the faults of these functional elements including said basic functional elements (P), spare functional elements (Sp), interconnecting elements (Cm) of these functional elements and a control unit, said method comprising:a step of positioning the functional elements of the logic network on the physical network;a routing step of programming interconnecting elements on the physical network, by choosing a maximum number of interconnecting elements which can be passed between two neighbouring processors using a shortest track search algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.