Synchronization of hardware and software debuggers
US6826717B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2001 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Aug 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A technique synchronizes logic signals captured in a PLD portion of a PLD system having both a microprocessor and PLD circuitry with executed instructions captured from a microprocessor portion. One or more signal lines connects the microcontroller portion with the PLD portion for transmitting signals between the two portions corresponding to debug operations in each portion.Conventional electronic circuits employing microprocessors and PLD's use independent debugging techniques, either of which are incapable of reflecting the complete state of the circuit at a selected time. Combined processor and PLD systems employ independent clocks for each portion, thus creating additional problems in synchronizing logic state traces in the PLD with the microprocessor instruction traces. The present invention provides a direct signals from the PLD portion to the microcontroller portion upon the occurrence of events relating to debugging and debug modes of the microprocessor. In one embodiment, the PLD portion is configured to send the output from a counter to a trace module in the microcontroller portion. The periodic and variably valued output signal from the PLD portion enables software in a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.