Data accelerator and methods for increasing data throughput
US6826721B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2001 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Jan 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31921
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A data accelerator for use in a test vector sequencer includes a data translator, a plurality of sequence memory devices, and a switch. The data translator and the switch are configured via a control signal responsive to an indication that a first sequence memory device is prepared to receive a data segment and that a second sequence memory device is prepared to transfer a previously stored data segment. The test sequencer forwards a first application segment to a first memory device and acquires a subsequent application with a second memory device, detects a condition responsive to the completion of the segment acquisition and forwarding tasks, switches the roles of the first and second memory devices, and repeatedly switches and detects until all application segments have been processed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.