Multi-rate reed-solomon encoders
US6826723B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2001 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Nov 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6516
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides for smaller, faster Reed-Solomon encoders, while at the same time providing support of multiple codes in a simple architecture having a reduced number of Galois field multipliers. In accordance with the principles of the present invention, a polynomial is factored differently than conventional Reed-Solomon encoders, resulting in enhanced performance, simplified circuitry, and/or a reduction of critical paths in the Reed-Solomon encoders. Thus, not only are the number of required Galois field multipliers reduced, but support for three different Reed-Solomon codes is provided with a minimized number of Galois field multipliers. In the disclosed embodiments, rather than implementing n subfilters each representing an individual degree polynomial filter as in Cox's conventional Reed-Solomon encoder, the present invention implements multiple degree polynomials factored in a way which is convenient to a desired plurality of Reed-Solomon codes. The polynomials may be divided into any degree subtrunks convenient for the particular application. One preferred embodiment supports up to three Reed-Solomon codes all within a single architecture, comprising only thr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.