Dual gate material process for CMOS technologies

US6828181B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jia Chen · Ossining, US
• Andreas Grassmann · Villach, AT

Key dates

• Filing date: May 8, 2003
• Grant date: Dec 7, 2004
• Expiry date: May 8, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177

Abstract

A method and structure for a method of manufacturing a device having different types of transistors, wherein gates of the different types of transistors in the device comprise different materials. The method comprises depositing a silicon layer on a gate dielectric layer, depositing a first-type gate material on the silicon layer, removing the first-type gate material from areas where a second-type gate is to be formed, depositing a second-type gate material on the silicon layer in areas where the first-type gate material was removed, and simultaneously patterning the first-type gate material and the second-type gate material into first-type and second-type gates, and anneal and transform the two types of gate materials.