Semiconductor member manufacturing method and semiconductor device manufacturing method
US6828214B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2002 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Oct 17, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/249953
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15′), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10′). This first substrate (10′) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.