Integrated structure
US6828651B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 5, 2001 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Jul 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.