Thick oxide P-gate NMOS capacitor for use in a phase-locked loop circuit and method of making same
US6828654B2 · kind B2 · utility
8Cited by
21References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 27, 2001 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Dec 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a low-pass filter for a phase locked loop (PLL) circuit, a capacitor formed by an N-type substrate, a P-type region formed on the N-type substrate, a thick oxide formed over the P-type region, a P+ gate electrode formed over the thick oxide and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.