Substrate voltage connection
US6828682B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 6, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Aug 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate that includes a non-electrically conductive core having a first side and an opposing second side. A first electrically conductive layer is disposed on the first side of the core, and a second electrically conductive layer is disposed on the second side of the core. Electrically conductive core vias extend from the first side of the core to the second side of the core. The core vias are disposed in an array. An electrically conductive contact is formed on an upper build-up layer on the first side of the core, and overlies the array of core vias. A first electrically conductive via electrically connects the contact to an intervening build-up layer disposed between the upper build-up layer and the first electrically conductive layer. The first via overlies the core via array. A second electrically conductive via electrically connects the intervening build-up layer and the first electrically conductive layer, where the second electrically conductive via is not disposed over the core via array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.