High-speed memory system
US6828819B2 · kind B2 · utility
5Cited by
8References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Jan 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a chipset mounted on a circuit board, and first and second memory module connectors mounted respectively on the circuit board. The first and second memory modules are inserted into the first and second memory module connectors, respectively. The memory system further includes a bus connected to the chipset and the first and second memory module connectors so to create a branch point. Each of the first and second memory modules includes at least one memory device connected to the bus via a stub line and a stub resistor. Impedance of the bus is less than that of the stub line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.