Heterogeneous interconnection architecture for programmable logic devices
US6828824B2 · kind B2 · utility
65Cited by
25References
18Claims
0Family size
Assignee
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Key dates
| Filing date | May 30, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | May 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.