Low-jitter loop filter for a phase-locked loop system
US6828864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Jul 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A loop filter device and method for implementing a loop filter for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.