High noise rejection voltage-controlled ring oscillator architecture
US6828866B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 6, 2003 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Oct 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00208
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. ‘Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g., a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e.g., a ground terminal). The first and second current sources reduce the coupling of noise from the first power s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.