Successive approximation analog-to-digital converter with pre-loaded SAR registers
US6828927B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2002 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Nov 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. A method for performing an enhanced SAR conversion is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.