Magnetic ram cell with amplification circuitry and MRAM memory array formed using the MRAM cells
US6829160B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2002 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Feb 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetic random access memory (MRAM) cell and a memory array formed from the MRAM cells are disclosed. The MRAM cell includes a magnetic tunneling junction and a transistor. The magnetic tunneling junction includes a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The gate of the transistor is coupled to a first end of the magnetic tunneling junction. The source of the transistor is coupled to a second end the magnetic tunneling junction. The drain of the transistor is coupled with an output for reading the magnetic memory cell. During reading, a read current is applied to the magnetic tunneling junction and the transistor is preferably operated in a saturation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.