High speed multi-stage switching network formed from stacked switching layers
US6829237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2001 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Dec 26, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/93
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A compact multi-stage switching network (100), and a router (510) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports (110) to selected ones of a second plurality of output ports (190) comprising: a first stack (140) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit (142); a second stack (160) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer (113) containing at least one switching element circuit (162); and interconnecting circuitry (150) that connects the first stack (140) of IC layers to the second stack (160) of IC layers to form the compact multi-stage switching network. The stacks (140, 160) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection. Also contemplated are the use of superconducting IC switching circuits (142) and a suitable superconducting cooling housing (730), as permitted by the compact nature of the multi-stage switching network (100), in order…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.