Complex valued delta sigma phase locked loop demodulator
US6829311B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2000 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Aug 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D3/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A complex valued delta sigma Phase Locked Loop (PLL) demodulator. The demodulator is a multiple stage demodulator. The first stage is a conversion stage which converts an incoming signal into a first complex representation. The second stage is a direct digital synthesizer (DDS)/mixer which synthesizes a signal to be mixed with the first complex signal and performs the mixing operation to produce a second complex output. This second complex signal is controlled by a bitstream fed back from the third stage—a phase quantizer stage. The bitstream represents the quantized phase difference between the synthesized signal and the first complex signal. The DDS/mixer stage then measures the synthesized signal for any phase difference from the incoming signal through the feedback inherent to a PLL, the bitstream thus provides an output that gives the frequency of the desired signal. As a side benefit, the real component of the second complex signal, provides an amplitude estimate of the desired signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.