Next snoop predictor in a host controller
US6829665B2 · kind B2 · utility
10Cited by
21References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Nov 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which implements a snoop-based coherency scheme. The acts of snooping a bus for a first address and searching a posting queue for the next address to be snooped are performed simultaneously to minimize the request cycle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.