Inductance and via forming in a monolithic circuit
US6830970B2 · kind B2 · utility
10Cited by
14References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 10, 2002 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Oct 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing, in a monolithic circuit including a substrate, an inductance and a through via, including the step of forming, from a first surface of the substrate, at least one trench according to the contour of the inductance to be formed; forming by laser in the substrate a through hole at the location desired for the via; simultaneously insulating the surface of the trench and of the hole; and depositing a conductive material in the trench and at least on the hole walls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.