Power MOS transistor for absorbing surge current
US6831331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2001 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Sep 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
Abstract
A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.