Graphics pixel packing for improved fill rate performance
US6831653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2001 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Feb 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for packing pixels together to provide a increased fill rate in a frame buffer hardware in the graphics system. The graphics system may be configured to receive and rasterize graphics data at a faster cycle rate than the system's frame buffer memory fill rate. The output from the rasterization hardware may be stored in a FIFO memory that is configured to selectively shift pixels in order to improve fill rate performance. The FIFO memory may be configured to ensure that the pixels meet certain criteria in order to prevent page faults and interleave conflicts that could reduce the fill rate. The FIFO memory may also be configured to remove empty cycles that occur as a result of the pixel packing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.