Byte aligned redundancy for memory array
US6831868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2002 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Dec 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes byte aligned column redundancy capabilities for use in repairing the memory when a defective column is present. The memory array includes a repair/redundant column for use in repairing the memory when another column of the memory array is defective. The memory also has a redundant write multiplexer to select, when a defective column is present in the memory array, an input data bit to be written to the redundant column. A first input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the first column group and a second input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the second column group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.