Effective protocol for high-rate, long-latency, asymmetric, and bit-error prone data links
US6831912B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2000 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Mar 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/18
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for efficiently and reliably communicating over a high-speed asymmetric communications link. The system includes a first mechanism for connecting a first device to a second device via a channel. A second mechanism delivers data packets over the channel from the first device to the second device. Each packet is associated with a window of packets. A third mechanism selectively employs the second mechanism to re-send data packets not received by the second device after each window of packets. The window of packets is sized in accordance with the bandwidth of the communications link between the first device and the second device, and the round trip delay time. In a specific embodiment, the first mechanism (includes Transmission Control Protocol/Internet Protocol (TCP/IP) functionality on the first device and the second device for establishing a first TCP/IP link from the second device to the first device. The first mechanism also includes Universal Datagram Protocol (UDP) functionality on the first device and the second device for transferring UDP packets from the first device to the second device. The third mechanism sends acknowledgement messages from the second device to t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.