Method for reducing noise in integrated circuit layouts
US6832180B1 · kind B1 · utility
9Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1999 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Oct 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for minimizing noise in an integrated circuit is described, the method including choosing a net to be analyzed, determining that the total path length of conductive paths coupled to a driver within the net exceed a maximum acceptable length for that given driver according to the minimum acceptable noise levels for that given net, and inserting at least one buffer within the net at a position which is within the maximum acceptable length for conductive paths coupled to the driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.