System, method and computer program product for mapping system memory in a multiple node information handling system
US6832304B2 · kind B2 · utility
2Cited by
18References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2002 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Jan 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method, and computer program product for detecting a first memory in a first node and detecting a second memory in a second node coupled to the first node. The system, method, and computer program product ensure that a first set of contiguous addresses is mapped to a portion of the first memory where the first set of contiguous addresses each have a value lower than a four gigabyte address, and ensure that a second set of contiguous addresses is mapped to a portion of the second memory where the second set of contiguous addresses each have a value lower than the four gigabyte address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.