Device on a source synchronous bus sending data in quadrature phase relationship and receiving data in phase with the bus clock signal
US6832325B2 · kind B2 · utility
23Cited by
6References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Jul 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device on a source synchronous data bus includes a clock generation circuit which generates transmit and receive clock signals for transmitting and receiving data. The device sends data in quadrature phase relationship with the bus clock signal and receives data in phase with the bus clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.