Cache thresholding method, apparatus, and program for predictive reporting of array bit line or driver failures
US6832329B2 · kind B2 · utility
32Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2001 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Dec 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided for predicting cache array bit line or driver failures. This mechanism checks for five consecutive errors at different addresses within the same syndrome on invocation of event scan polling to characterize the failure. Once the failure is characterized, it is reported to the system for corrective maintenance including dynamic and/or boot time processor deconfiguration or preventive processor replacement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.